The present invention disclosed herein relates to a semiconductor storage device and a method for operating the same.
As disclosed in Japanese Patent Laid-open Publication No. 2002-8386 (hereinafter, referred to as a cited document 1), one of a plurality of bit lines constituting a memory array in a nonvolatile semiconductor memory is selectively connected to one of main bit lines, and one of a plurality of main bit lines is selectively connected to one of data lines. In addition, a sensing signal input terminal of a differential amplifier constituting a sensing circuit is connected to a sensing line connected to the data line, and a reference signal input terminal is connected to a reference sensing line. In this way, data read from a memory cell is determined.
In the differential amplifier constituting the sensing circuit, it is difficult to exactly balance a capacitance of the reference sensing line and a capacitance of the sensing line in view of read speed and resistance to noise. Since capacitances are placed at different positions, the differential amplifier is weak against noise and has a limitation in view of an area.
As one of approaches to solving those limitations, the cited document 1 provides a memory cell in which first and second memory cells are arranged, and first and second column trees including line groups through which data of the first and second memory cells are transferred. When the first memory cell is selected, a capacitance balance is obtained by connecting the first column tree to the sensing signal input terminal of the differential amplifier and connecting the second column tree to the reference signal input terminal.
FIG. 2 is a memory block diagram illustrating a memory array configuration obtaining a capacitance balance of an input terminal of a differential amplifier. Referring to FIG. 2, a first column tree is a line group through which data of a first memory cell is transferred. The first column tree includes a first intermediate data line IDL01, main bit lines MBL0-01 and MBL1-01, and bit lines Bi:BL0, Bi:BL1, Bi:BL4, Bi:BL5, Bj:BL0, Bj:BL1, Bj:BL4 and Bj:BL5. Memory cells (not shown) are connected to the bit lines BL.
A second column tree is a line group through which data of another memory cell is transferred. The second column tree includes a second intermediate data line IDL23, main bit lines MBL0-23 and MBL1-23, and bit lines Bi:BL2, Bi:BL3, Bi:BL6, Bi:BL7, Bj:BL2, Bj:BL3, Bj:BL6 and Bj:BL7. Like the first column tree, memory cells (not shown) are connected to the bit lines BL.
When a memory cell inside the first column tree is read, a column switching gate 0101 connects the first column tree and the second column tree, respectively, to a data line DL and a reference data line RDL in response to a first column switching signal SW01. In addition, when a memory cell inside the second column tree is read, the column switching gate 0101 connects the second column tree and the first column tree, respectively, to the data line DL and the reference data line RDL in response to a second column switching signal SW23.
The data line DL is connected to the sensing signal input terminal of the differential amplifier inside the sensing circuit, and the reference data line RDL is connected to the reference signal input terminal. The sensing circuit will be described later. Of the first and second column trees, the column tree including the read-selected memory cell is connected to the data line DL, and the non-selected column tree is connected to the reference data line RDL. Since the first and second column trees have the same configuration, the capacitances of the trees are equal to each other. That is, it is possible to make the capacitance of the data line DL equal to the capacitance of the reference data line RDL.
FIG. 3 is a circuit diagram of a sense amplifier circuit. Referring to FIG. 3, the sense amplifier circuit 200 is a circuit which determines data read through the data line DL and the reference data line RDL of FIG. 2. The sense amplifier circuit 200 includes a separation circuit 50-2 applying a predetermined bias so that the voltage of the data line DL does not exceed a predetermined voltage, a load circuit 30-2 operating as a load between the sensing line SA and the data line DL and between the reference sensing line RSA and the reference data line RDL, a differential amplifier 20 determining read data by amplifying a slight voltage difference between the sensing line SA and the reference sensing line RSA, and an output buffer circuit 10 temporarily storing data determined by the differential amplifier 20.
Gates of separation NMOS transistors 51 and 52 of the separation circuit 50-2 are connected to a bias line BIAS. A source of the NMOS transistor 51 is connected to the reference data line RDL, and a source of the NMOS transistor 52 is connected to the data line DL. Also, the source of the NMOS transistor 51 is connected to a drain of an NMOS transistor 56, and a source of the NMOS transistor 56 is grounded. A gate of the NMOS transistor 56 is connected to a reference voltage signal line VREF. The separation circuit 50-2 includes an NMOS transistor 54 for equalization. Both terminal of the NMOS transistor 54 are connected to NMOS transistors 53 and 55 for capacitance balance, and a gate of the NMOS transistor 54 is connected to an equalization signal line EQ. Sources and drains of the NMOS transistors 53 and 55 for capacitance balance are shorted and connected to the reference data line RDL and the data line DL, respectively. A reference current source (not shown) is connected to the reference data line RDL.
In PMOS transistors 35 to 38 constituting the load of the load circuit 30-2, the PMOS transistor 35 has a source connected to a power supply voltage line VCC, and a gate and a drain connected to a source of the PMOS transistor 36. The PMOS transistor 36 has a gate connected to a load enable signal LOADEN, and a drain connected to the drain of the separation NMOS transistor 51. Likewise, the PMOS transistor 37 has a source connected to the power supply voltage line VCC, and a gate and a drain connected to a source of the PMOS transistor 38. The PMOS transistor 38 has a gate connected to the load enable signal line LOADEN, and a drain connected to the gate of the separation NMOS transistor 52.
A source of a PMOS transistor 31 and a source of a PMOS transistor 33 are connected to the power supply voltage line VCC, and their gates are connected to an enable inversion signal line nEN. A drain of the PMOS transistor 31 is connected to a source of a PMOS transistor 32, and a drain of a PMOS transistor 33 is connected to a source of a PMOS transistor 34. Gates of the PMOS transistors 32 and 34 are connected to a gate of the PMOS transistor 32 to thereby form a mirror circuit, and are connected to the drain of the separation NMOS transistor 51. A drain of the PMOS transistor 34 is connected to the drain of the separation NMOS transistor 52.
The load circuit 30-2 includes an equalization PMOS transistor 40. Both terminals of the equalization PMOS transistor 40 are connected to capacitance balance PMOS transistors 39 and 41, and gates of the equalization PMOS transistor 40 is connected to an equalization inversion signal line nEQ. Sources and drains of the capacitance balance PMOS transistors 39 and 41 are shorted and connected to the drains of the separation NMOS transistors 51 and 52, respectively. The load circuit 30-2 includes capacitance balance PMOS transistors 42 to 44. Sources and drains of the capacitance balance PMOS transistors 42 and 43 are shorted and connected between the drain of the PMOS transistor 36 and the drain of the NMOS transistor 51 and between the drain of the PMOS transistor 38 and the drain of the NMOS transistor 52, and gates of the capacitance balance PMOS transistors 42 and 43 are connected to the drain of the PMOS transistor 38. Likewise, a source and a drain of the PMOS transistor 44 are shorted and connected to the power supply voltage line VCC, and a gate of the PMOS transistor 44 is connected to a connection node of the PMOS transistors 42 and 43.
A PMOS transistor 21 of the differential amplifier 20 has a source connected to the power supply voltage line VCC, and a gate connected to the enable inversion signal line nEN. PMOS transistors 22 and 24 have sources connected to a drain of the PMOS transistor 21, and a gate connected to drains of NMOS transistors 23 and 25. Gates of the PMOS transistors 22 and 24 are connected to the drains of the PMOS transistors 38 and 36 through the sensing line SA and the reference sensing line RSA, respectively. The NMOS transistors 23 and 25 have sources grounded, and gates connected to the drain of the NMOS transistor 25, thereby forming a mirror circuit. The equalization NMOS transistor 26 has a drain and a source connected to the drains of the PMOS transistors 22 and 24, and a gate connected to the equalization signal line EQ.
An input terminal of an inverter 11 of the output buffer circuit 10 is connected to a connection node of the drains of the PMOS transistors 22 and 23, and an output terminal of the inverter 11 is connected to an output signal line nSAOUT.
A read operation will be described below. Referring to FIG. 2, a first column selection decoder 0102 decodes a column selection internal address signal to select and activate one of a plurality of first column selection signals Bi:H0 to Bi:H3 and Bj:H0 to Bj:H3. One of first column gates 0103-Bi:0 and 0103-Bj:1 is turned on, so that one of the bit lines Bi:BL0 to Bi:BL3 and Bj:BL0 to Bj:BL3 is connected to the main bit lines MBL0-01 and MBL0-23. Simultaneously, one of the first column gates 0103-Bi:1 and 0103-Bj:1 is turned on, so that one of the bit lines Bi:BL4 to Bi:BL7 and Bj:BL4 to Bj:BL7 is connected to the main bit lines MBL1-01 and MBL1-23.
A second column selection decoder 0104 decodes a column selection internal address signal to select and activate one of a plurality of second column selection signals D0 and D1. One of the main bit lines MBL0-01 and MBL1-01 is connected to the first intermediate data line IDL01. Simultaneously, one of the main bit lines MBL0-23 and MBL1-23 is connected to the second intermediate data line IDL23.
A column switching selection decoder 0106 decodes the column selection internal address signal to select one of the first column switching signals SW01 and SW23.
When a memory cell inside the first column tree is selected, the switching signal SW01 is high and the switching signal SW23 is low. Therefore, the first intermediate data line IDL01 is connected to the data line DL and simultaneously the second intermediate data line IDL23 is connected to the reference data line RDL.
When a memory cell inside the second column tree is selected, the switching signal SW01 is low and the switching signal SW23 is high. Therefore, the second intermediate data line IDL23 is connected to the data line DL and simultaneously the first intermediate data line IDL01 is connected to the reference data line RDL. That is, the column tree including the read-selected memory cell is connected to the data line DL and data signal of the memory cell is transferred. The non-selected column tree is connected to the reference data line RDL so that the capacitance balance is obtained.
Referring to FIG. 3, a read data signal is received by connecting the source of the separation NMOS transistor 51 of the separation circuit 50-2 to the reference data line RDL, and connecting the source of the separation NMOS transistor 52 to the data line DL. Before receiving the read data signal, the gates of the equalization NMOS transistor 54, the equalization NMOS transistor 40, and the equalization NMOS transistor 20 included in the separation circuit 50-2, the load circuit 30-2, and the differential amplifier 20 receive the equalization signal EQ or the equalization inversion signal nEQ to set a potential of each node to an equal level. In this case, the gate capacitance of the capacitance balance PMOS transistors 42 to 44 are set to be equivalent to the gate capacitance of the PMOS transistors 32 and 34 constituting the mirror circuit, and the capacitance accompanying the load circuit 30-2 is balanced.
When the selected memory cell is an on cell retaining data “1”, the read data signal is transferred to the sensing line SA through the data line DL. The reference current source connected to the reference data line RDL is set to half the current amount flowing from the on cell. Thus, the current is amplified while passing through the separation NMOS transistors 51 and 52, so that the sensing line SA becomes a low level and the reference sensing line RSA becomes a high level in the load circuit 30-2. The voltage difference is amplified by the differential amplifier 20 and is output as data “1” through the output buffer circuit 10 to the output signal line nSAOUT.
When the selected memory cell is an off cell retaining data “0”, no current flows through the memory cell. Thus, the voltage of the data line DL is higher than that of the reference data line RDL. The voltage is amplified while passing through the separation NMOS transistors 51 and 52, so that the sensing line SA becomes a high level and the reference sensing line RSA becomes a low level in the load circuit 30-2. The voltage difference is amplified by the differential amplifier 20 and is output as data “0” through the output buffer circuit 10 to the output signal line nSAOUT.
In such a structure, however, since the column switching gates 0101 are arranged between the first and second column trees and the sensing circuit 200, independent circuits for the column switching gates are required. Consequently, an additional layout area is also required. That is, the circuit and chip area are increased, leading to increase of design and chip costs.